1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to optimized layout design and fabrication techniques for making standard core cells used to design integrated circuit chips and application specific integrated circuit (ASIC) devices.
2. Description of the Related Art
As the demand for smaller and more efficient integrated circuit devices continues to grow, an even greater demand is placed on layout design engineers to develop new designs and processes. Because the complexity and density of integrated circuit designs have become quite complex, a common technique for designing integrated circuit designs is to use modeling software languages. The most popular and commonly used modeling software language is a hardware description language (HDL) named xe2x80x9cVerilogxe2x80x9d (IEEE Verilog Standard 1364, 1995). Using Verilog, designers are able to describe each component of an integrated circuit in terms of its functional behavior as well as its implementation. Once a circuit design using Verilog is complete, the Verilog code is synthesized to generate what is called a xe2x80x9cnetlist.xe2x80x9d A netlist is essentially a list of xe2x80x9cnets,xe2x80x9d which specify components (know as xe2x80x9ccellsxe2x80x9d) and their interconnections which are designed to meet a circuit design""s performance constraints.
However, the actual placement plan of components on silicon and the topography of wiring is reserved for a subsequent xe2x80x9clayoutxe2x80x9d stage. In the layout stage, another software tool, commonly referred to as xe2x80x9cplace and routexe2x80x9d software, is used to design the actual wiring that will ultimately interconnect the cells together. To do this, each cell typically has one or more xe2x80x9cpinsxe2x80x9d for interconnection with pins of other cells. The xe2x80x9cnetlistxe2x80x9d therefore defines the connectivity between pins of the various cells of an integrated circuit device.
Traditionally, the xe2x80x9cplace and routexe2x80x9d software tools can either be used to design each and every one of a transistor""s geometric layout interconnections (i.e., wiring) in order to fabricate the desired circuit, or alternatively implement some xe2x80x9cpre-designedxe2x80x9d layout cells. When pre-designed layout cells are used, the layout process is somewhat simplified because the bulk of the design work will only require laying out the geometric features that define the metallization interconnect lines and conductive vias of the various layers of a silicon chip. Although the use of pre-designed cells has been implemented for some time, the fabrication techniques and materials used to fabricate metallization interconnect lines has unfortunately remained stagnate.
For example, in the fabrication of semiconductor devices, various impurity implants and transistor isolation structures are first fabricated into the wafer. Next, the CMOS transistor structures, including their polysilicon gates, drains and sources are defined. Once the basic transistor structures are fabricated throughout the wafer, a dielectric layer is deposited over the transistor structures. At this point, conductive vias are formed in the dielectric layer before a first metallization layer (M-1) is blanket deposited. The first metallization layer is then patterned using standard photolithography techniques in order to define the desired geometric interconnections. This process is then repeated for as many subsequently layers as needed to complete the interconnections of the integrated circuit device. Although the place and route software is capable of generating a proposed wiring solution, the layout efficiency of the software tool is usually restricted by the complexity of the design and chip area constraints imposed by following rigid metallization wiring standards.
Traditionally, each metallization layer (M-1 through the highest metal layer) in a design is made from an aluminum-based material, which is known to have problems with electromigration. Although many techniques involving the addition of sophisticated barrier materials have been developed to combat the electromigration problem, the fabrication of additional barrier layers and materials does have the disadvantage of adding more complexity and cost to the fabrication of a given integrated circuit design.
In view of the foregoing, there is a need for new layout and fabrication techniques that simplify layout designs for complex integrated circuits. The is also a need for new standard cell designs that facilitate more dense designs and that implement materials that are more resistant to electromigration problems.
Broadly speaking, the present invention fills these needs by providing new standard cell designs that enable place and route software to design more complex and densely arranged circuits. The present invention also provides new standard cell designs that implement local interconnect materials to complete the lower level transistor interconnections to achieve a higher density design. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a semiconductor standard cell architecture is disclosed. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit. In a preferred embodiment, the local interconnect metallization lines are configured to be fabricated from a high resistivity metal having a resistivity that is greater than aluminum containing metals/alloys.
In yet another embodiment, a semiconductor cell having a standard architecture is disclosed. The semiconductor cell is part of a library of cells that are accessible to a place and route layout tool that can be programmed to complete a semiconductor functional circuit on a semiconductor chip. The semiconductor cell includes a plurality of diffusion regions that designate source and drain regions of transistors of the semiconductor functional circuit. A polysilicon layout defining gate electrodes and interconnections of the semiconductor functional circuit. A local interconnect metallization layout that is patterned to define a plurality of local interconnect metallization lines that are configured to substantially interconnect selected ones of the source and drain regions and gate electrodes to at least partially define the semiconductor functional circuit. The local interconnect metallization layout is configured to be embodied in a material having a resistivity of at least about 0.1 ohms/square. In a most preferred embodiment, the material having the resistivity of at least 0.1 is tungsten.
In still another embodiment, a method for making a semiconductor cell having a standard architecture is disclosed. The semiconductor cell is designed to be part of a library of cells that are accessible to a place and route layout tool that uses the semiconductor cell to complete a semiconductor functional circuit that is to be fabricated on a semiconductor chip. The method includes: (a) defining a plurality of diffusion regions that designate source and drain regions of transistors of the semiconductor cell; (b) defining a polysilicon layout that identifies gate electrodes and interconnections of the semiconductor cell; and (c) defining a local interconnect metallization layout that is patterned to identify a plurality of local interconnect metallization lines that are configured to substantially interconnect selected ones of the source and drain regions and gate electrodes to at least partially define the semiconductor cell. The local interconnect metallization layout is preferably configured to be physically embodied in a material having a resistivity that is greater than that of aluminum. In another aspect of this embodiment, the method further includes designing local interconnect pins from the plurality of local interconnect metallization lines that enable an interconnection of the semiconductor cell to another semiconductor cell. In yet another aspect of this embodiment, the method includes designing local interconnect power buses from the plurality of local interconnect metallization lines.
Advantageously, the various embodiments of the present invention provide standard cell architectures that enable the fabrication of more compact cells, which are used in the design and fabrication of semiconductor chips. The strategic implementation of local interconnect metallization as the lowermost routing level also solves the prior art problems associated with aluminum electromigration. Additionally, the local interconnect metallization layout is designed to implement xe2x80x9cpinxe2x80x9d connections, which are used by suitable place and route software tools. The local interconnect metallization is also capable of being implemented for local power buses xe2x80x9cVssxe2x80x9d and xe2x80x9cVddxe2x80x9d. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.